Static random access memories (SRAMs) are sometimes used in preference to dynamic random access memories (DRAMs) because SRAMs have faster access times, they require no refresh circuitry and they can be made to have very low power consumption. However, conventional SRAMs are more expensive than DRAMs because an SRAM uses a large number of transistors compared to a DRAM. Hence, DRAMs are preferred in applications where the cost per bit of memory is important.
There are two types of SRAM memory cells in general use today--a six transistor (6T) cell and a four transistor (4T) cell. A typical 6T cell, illustrated in FIG. 1, consists of a latch made up of two cross coupled CMOS inverters, which form a circuit known as a flip-flop. In this cell, the load devices Q3 and Q4 are p-channel transistors. The pull down transistors, Q5 and Q6, and the access transistors, Q1 and Q2, are n-channel transistors. (The term "pull down" derives from the fact that the output nodes of these transistors are pulled down to substantially ground potential when the transistors are biased to conduction.) The first access transistor Q1, the gate of which is controlled by word line WL, provides selective coupling of the true bit line D to storage node A. A second access transistor Q2, the gate of which is also controlled by word line WL, provides selective coupling of the complement bit line D' to storage node B. Since very little power is required to maintain a latched state, 6T SRAMs are often used for memory in battery applications. 6T SRAMs are the most costly SRAMs to manufacture because the 6T cell uses the greatest amount of chip real estate.
A typical 4T SRAM cell, illustrated in FIG. 2, is similar to the 6T cell of FIG. 1 except that the two p-channel load transistors are replaced by resistive elements, R3 and R4. A 4T SRAM is usually less costly to produce than a 6T SRAM because more memory cells can be packed onto each chip. 4T SRAMs are, however, disadvantageous in very low power applications because the resistors consume more current than the p-channel transistors they replace.
In order to overcome the above problems associated with conventional SRAMs, a three transistor (3T) SRAM memory cell was developed. This new SRAM memory cell is described and claimed in my commonly owned and copending application Ser. No. 08/388,873, entitled "Three Transistor Static Random Access Memory Cell", filed Feb. 14, 1995, incorporated herein by reference. The preferred embodiment of the 3T SRAM described in detail in this copending application combines a DRAM memory cell with a half latch. That SRAM memory cell circuitry includes an access transistor coupled to a capacitor, an n-channel pull down transistor and a p-channel thin film transistor (TFT) which acts as the capacitor pull up device. The gate of the TFT is formed in the same layer of polysilicon in which the capacitor storage node is formed. The source, drain and channel of the p-channel TFT is formed in a separate layer of polysilicon. The gate of the TFT is coupled to the supply voltage V.sub.cc through back to back diodes, which function as a resistor, and to ground or a substrate voltage through the pull down transistor.
The present invention is directed to a set of cross coupled thin film transistors that are formed on top of one another in vertically adjacent layers of polysilicon. This structural configuration saves valuable chip real estate and, correspondingly, allows for reduced manufacturing costs. When used in the memory cell described in my copending application, the first TFT functions as the capacitor pull up device and the second TFT functions as an active load device in place of the back to back diodes described as part of the preferred embodiment in my copending application. Using a TFT instead of back to back diodes as the load device increases the speed of read and write operations in the SRAM. The invented TFT cross coupling structure allows this increase in speed without adding to cell size.